Pulse width modulation (PWM) techniques are used to control voltage-source inverters (VSI), in applications such as control of DC brushless, AC induction and permanent-magnet synchronous motors, and other loads. Three-phase (3.phi.) VSIs are common, but VSIs have configurations for different numbers of phases, and PWM techniques are used to control such systems, as well. PWM inverters make it possible to control both the frequency and magnitude of the voltage and current applied to a load, such as a motor for example. As a result, PWM inverter-powered motor drives offer better efficiency and higher performance compared to fixed frequency motor drives. The energy that a PWM inverter delivers to a load is controlled by PWM signals applied to the gate of the power transistors.
Several PWM techniques are known and used in the art, for determining the modulating signal and the switch-on/switch-off instants from the modulating signal. Currently popular examples are sinusoidal PWM, hysteric PWM, and space-vector (SV) PWM. These techniques are used for control of AC induction, Brushless DC (BLDC) and switched reluctance (SR) motors.
PWM can be either symmetric, or asymmetric, as shown in FIG. 1. In FIG. 1 two pulse waveforms 10 and 12, are shown for four contiguous, equal periods. The top waveform 10 in the figure is an example of an asymmetric PWM, in which the timing for the leading edge in each period varies, as shown by arrow 14, while the trailing edge always coincides with the end of the period. The bottom waveform 12 in the figure is an example of a symmetric PWM, in which the timing for both the leading edge and the trailing edge is varied by the same amount in opposite directions, as shown by arrows 16 and 18, respectively, resulting in symmetry for the waveform in every period.
A circuit diagram of a typical 3.phi. VSI 20 is shown in FIG. 2. A DC voltage, V.sub.DC, is provided between a V+.sub.BUS 22 and a V-.sub.BUS 24. Three legs are connected between bus 22 and bus 24. The first leg includes a power transistor Q1 having its collector connected to bus 22, and a power transistor Q2 having its collector connected to the emitter of transistor Q1 and having its emitter connected to bus 24. A diode D1 is connected between the emitter and collector of transistor Q1, and a diode D2 is connected between the emitter and collector of transistor Q2. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal a is provided on line 26 to the base of transistor Q1, while a control signal a' is provided on line 28 to the base of transistor Q2. The common connection point of transistors Q1 and Q2 is connected to line 38, which carries the output voltage V.sub.a and supplies the phase current i.sub.a of the first leg.
The other two legs are of the same structure as the first leg. Thus, the second leg includes a power transistor Q3 having its collector connected to bus 22, and a power transistor Q4 having its collector connected to the emitter of transistor Q3 and having its emitter connected to bus 24. A diode D3 is connected between the emitter and collector of transistor Q3, and a diode D4 is connected between the emitter and collector of transistor Q4. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal b is provided on line 30 to the base of transistor Q3, while a control signal b' is provided on line 32 to the base of transistor Q4. The common connection point of transistors Q3 and Q4 is connected to line 40, which carries the output voltage V.sub.b and supplies the phase current i.sub.b of the second leg.
Similarly, the third leg includes a power transistor Q5 having its collector connected to bus 22, and a power transistor Q6 having its collector connected to the emitter of transistor Q5 and having its emitter connected to bus 24. A diode D5 is connected between the emitter and collector of transistor Q5, and a diode D6 is connected between the emitter and collector of transistor Q6. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal c is provided on line 34 to the base of transistor Q5, while a control signal c' is provided on line 36 to the base of transistor Q6. The common connection point of transistors Q5 and Q6 is connected to line 42, which carries the output voltage V.sub.C and supplies the phase current i.sub.c of the third leg.
In operation, when an upper transistor, Q1, Q3 or Q5, is turned on, i.e., when a, b or c is 1, the corresponding lower transistor, Q2, Q4, or Q5, is switched off, i.e., the corresponding a', b' or C' is 0.
In operating a VSI, such as 3.phi. VSI 20 of FIG. 2, it is important to control the phase currents, e.g. to control the torque and speed of a motor under control of the VSI. Therefore, it is important to know the phase currents.
The easiest way in which to monitor phase current is with a transformer coupled circuit. A hall effect sensor is typically used when this type of monitoring is chosen. However, such monitors are costly, requiring typically a transformer and separate integrated circuit. In addition, the signal output of such monitors requires a linear amplifier, which adds design complexity and further cost.
Another approach uses a so-called shunt resistor. An example of this is shown in FIG. 3, which is a diagram of the second, Q3, Q4 leg of the 3.phi. VSI 20 of FIG. 2, having the shunt resistor R.sub.S, connected between the base of transistor Q4 and V-.sub.BUS 24. Each of the three legs is provided with such a resistor. In using this technique the voltage v.sub.S across R.sub.S is measured when transistor Q4 is on, and Ohms Law applied to derive the current is through resistor R.sub.S. Now, the duty cycle of the particular leg determines the amount of time that the lower transistor in that leg, e.g., transistor Q4, is on. Ignoring dead band effects, if the duty cycle of a leg is d, expressed as a decimal quantity with a 0% duty cycle being represented as 0 and a 100% duty cycle being represented as 1.0, and the PWM period being represented as T.sub.PWM, then the upper transistor is on d* T.sub.PWM, and the lower transistor is on (1-d)*T.sub.PWM.
It is necessary for the width of the lower leg pulse, or, sampling interval, to be sufficiently long to have a "good" sample to measure. This is because reactive components at the base of the lower leg transistor will subject the voltage at that node to a time constant factor, delaying the achievement of the full voltage, causing ringing, and the like. The dead band included to prevent shoot through fault also reduces the effective sampling interval. Thus, the pulse width must be sufficiently long to take into account the dead band and still allow the measured voltage to settle, and thus correspond to the true motor phase current.
One prior art approach to dealing with this problem has been to "over-design" the inverter, so that the on time for the lower transistor e.g., transistor Q4, is never smaller than a lower bound. In other words, the inverter components are designed to provide a high enough voltage so that the upper transistor in any leg is never on for such a high portion of a PWM period that the lower transistor is on for such a short time that a good sample of the voltage V.sub.S cannot be taken.
However, even with an over-designed inverter, the direct approach of sampling the phase current when the lower transistor is on results in noise problems, because of the high dv/dt and di/dt caused by the switching of the high voltages and high currents in a PWM inverter. The high dv/dt and di/dt not only cause the voltage across the shunt resistor to have spikes, but also inject noise into the entire shunt output sampling circuit.
It is therefore an object of the present invention to provide a low cost solution to inverter phase current sensing that reduces noise in sensed phase current and does not require over-design of the inverter.